Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Table 2

Floorplanning optim of GA compared with hybrid algorithm.

Circuit	Number of blocks	GA		Hybrid
		Wirelength	CPU time	Wirelength	CPU time
xerox	10	33.56	30	32.06	26
Ami33	33	35.44	30	34.39	24
apte	9	25.48	30	24.23	22
Ami49	49	63.55	175	58.33	150
hp	11	28.46	45	27.54	60