A Probabilistic Spatial Distribution Model for Wire Faults in Parallel Network-on-Chip Links

Figure 1

(a) Demonstration of the PFLRM functionality under all three phases of recovery, using a 5-bit flit width, a faulty wire clustering of 2, and a total of 3 faulty wires (60% faulty wires). Stuck-at-one permanent faults are assumed. In phase 2-a the fault vector is rotated twice until all bits of vector equal 1, indicating a maximum fault clustering of 2. The boxed bit numbers under phase 3 indicate the respective newly recovered flit bits from the received and corrupted flit vector . The final two-position anticlockwise deshifting at the downstream router recovers the final flit to exactly equal to , the error-free flit being sent from the upstream router; the recovery phase takes 3 clock cycles () to complete (1 base plus 2 recovery cycles). (b) The five wires comprising the same parallel NoC link forming a virtual “ring.”

(a)

(b)