Research Article
High Real-Time Design of Digital Pulse Compression Based on FPGA
Table 4
Comparisons of DPC’s processing cycles with methods.
| FFT processors | Time | Comparisons with the proposed design |
| In place with single butterfly | 52656 | 35934↑ | Xilinx FFT IP | 24992 | 8270↑ | The proposed design | 16722 | — |
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