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Mathematical Problems in Engineering
Volume 2015, Article ID 870569, 11 pages
Research Article

High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem

1Electronics Department, University of Alcalá, Alcalá de Henares, 28805 Madrid, Spain
2School of Computing, Telecommunications and Networks, Birmingham City University, Millennium Point, Birmingham B4 7XG, UK

Received 2 December 2014; Revised 19 January 2015; Accepted 19 January 2015

Academic Editor: José R. C. Piqueira

Copyright © 2015 Ignacio Bravo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present a hardware implementation of the Jacobi algorithm to compute the eigenvalue decomposition (EVD). The computation of eigenvalues and eigenvectors has many applications where real time processing is required, and thus hardware implementations are often mandatory. Some of these implementations have been carried out with field programmable gate array (FPGA) devices using low level register transfer level (RTL) languages. In the present study, we used the Xilinx Vivado HLS tool to develop a high level synthesis (HLS) design and evaluated different hardware architectures. After analyzing the design for different input matrix sizes and various hardware configurations, we compared it with the results of other studies reported in the literature, concluding that although resource usage may be higher when HLS tools are used, the design performance is equal to or better than low level hardware designs.