A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

<table class="table-group" id="tab4"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td class="align_left"><span style="width: 6.6501ptpx;"><svg height="6.1673pt" id="M298" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 6.6501 6.1673" width="6.6501pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M495 86L479 114C446 82 419 66 409 66C401 66 401 72 406 97C420 166 436 231 453 297C489 435 454 448 428 448C406 448 384 439 354 422C305 394 222 327 161 247H159L183 345C200 415 194 448 173 448C143 448 82 410 23 351L38 325C64 349 95 371 105 371C111 371 116 365 109 336L25 -4L31 -12C50 -4 77 3 107 9C119 69 132 122 145 168C197 254 321 381 370 381C387 381 393 374 378 305L329 95C309 17 320 -12 345 -12C372 -12 430 19 495 86Z" id="g113-111"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="502" vert-adv-y="502"></glyph.data></g></svg></span></td><td class="align_center"> SIMD-x86 cycles</td><td class="align_center"> FPGA-tile-based cycles</td><td class="align_center"> DFSC cycles</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left">  32 </td><td class="align_center"> 16131 </td><td class="align_center"> 2081 </td><td class="align_center"> 1035</td></tr><tr><td class="align_left">64 </td><td class="align_center"> 130098 </td><td class="align_center"> 16417 </td><td class="align_center"> 8205</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

SIMD-x86 and FPGA-tile-based versus DFSC.

Mathematical Problems in Engineering

tab4

Table 4

Table 4: A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs 