Research Article  Open Access
CarrierBased PWM Method to Reduce CommonMode Voltage of ThreetoFivePhase Indirect Matrix Converter
Abstract
In order to reduce the commonmode voltage (CMV) for threetofivephase indirect matrix converter (IMC), the CMV with the conventional modulation strategy is analyzed. A novel carrierbased PWM (CBPWM) method is proposed in this paper. The zero vectors in the inverter stage are assigned to the rectifier stage, equivalently, which are not considered in the inverter stage. The zero vectors are selected appropriately to ensure that the dclink is connected to an input phase with the minimum absolute value, so that the larger CMV can be avoided. Then, the modulation signals are derived by the duty ratios, which are used to compare with the only one carrier signal and generate the gate pulses of switches. With the proposed method, the CMV is reduced effectively compared with the conventional modulation strategy. This method is analyzed and researched with a simulation model established by Matlab/Simulink. Simulation results are provided in detail to verify the feasibility and validity of the proposed method.
1. Introduction
With the rapid development of the power electronic converter, the drive system gradually gets rid of the bound of the phase number. Multiphase drive system has received more and more attention [1–5], so that the multiphase matrix converter (MC) has been widely studied [6–11]. The threetofivephase direct matrix converter (DMC) was proposed in [7], and there are fifteen bidirectional switches connected in series; each output phase can connect with each input phase. However, this topology requires many power switches, multistep commutation, and complicated overvoltage protection circuits [12]. To avoid the above problems, a threetofivephase indirect matrix converter (IMC) topology, illustrated in Figure 1, has been researched to implement the ACAC power converter. The benefits of threetofivephase IMC are similar to those of a threetofivephase DMC, such as no required large energy storage components, compact structure, bidirectional energy flow, unrestricted output frequency, a controllable input power factor, and a maximum voltage transfer ratio (VTR) of 0.7886 [7]. Moreover, it has additional advantages such as zero current safer commutation and less switching losses in the rectifier stage and less total number of power switches [11].
However, the CMV between the motor neutral point and the ground is caused inevitably when the SVPWM strategy is applied to MC. Due to the switches operating at high switching frequencies, the CMV, with a high value of , will produce a strong impact action on the motor drive system. Meanwhile, it will excite stray capacitance and parasitic coupling capacitance to generate highfrequency leakage current. This leakage current will produce a strong electromagnetic interference (EMI) [13–15]. Meanwhile, the CMV may cause shaft voltage between the shaft and the bearing seat through the distributed capacitance existing in the gap between stator, rotor, air, and ground, so that the normal operation of motor devices will be affected. Therefore, it is particularly important to reduce the negative effects of CMV.
At present, the research on control strategy to reduce CMV of the threetothreephase MC is relatively mature [14, 16–19], which is based on the mechanism of CMV. According to the amplitudefrequency characteristic of CMV, the lowpass filter with much smaller cutoff frequency than the switching frequency is applied in [16], so that the CMV is reduced. The high value of is suppressed in [17] by improving the topology of matrix converter, and the output voltage is not mutation. Instead of zero vectors, a pair of opposing active vectors is chosen in [18] to reduce CMV. The two smaller line voltages are selected in [14] to synthesize the dclink voltage. The CMV and switching losses of IMC are both reduced, but the maximum VTR is limited to 0.5. Using three active vectors to synthesize the desired output voltage vector is proposed in [19]. Although the CMV of IMC is reduced, the maximum VTR is only 0.577.
However, the research on CMV of the multiphase MC is relatively few. The zero vectors in the inverter stage are reselected based on SVPWM strategy in [20]. But it requires a complex sector combination and lookup tables.
In view of the above problems, a carrierbased PWM (CBPWM) method is proposed in this paper to reduce the CMV of threetofivephase IMC. This method focuses on the reasonable distribution of the zero vectors in both stages, so that the value of CMV is reduced. And the switching losses of the inverter stage are decreased.
2. Topology and Modulation Principles of ThreetoFivePhase IMC
2.1. Topology of ThreetoFivePhase IMC
The topology of threetofivephase IMC is shown in Figure 1. It consists of a rectifier stage with six bidirectional switches and a fiveleg inverter stage with ten unidirectional switches. , , and and , , and are threephase input voltages and input currents, respectively; , , , , and and , , , , and are fivephase output voltages and currents respectively. and are the dclink voltage and current, respectively. and are inductor and capacitor of input filter. The switches of the rectifier stage are denoted by using (; ), and those of the inverter stage are denoted by using ().
2.2. The Basic Principle of Conventional Modulation Strategy
For the rectifier stage, suppose the three input voltages are described bywhere and are the amplitude and angular frequency of the input phase voltage, respectively. One period of input phase voltages is divided into twelve segments, as shown in Figure 2.
(a) Input threephase voltages
(b) Input three line voltages
In each segment, to obtain the maximum dclink voltage , only two larger and positive line voltages are selected to synthesize [21]. Taking the input voltages in segment 1 as an example, then, the voltages and are selected, as shown in Figure 2(b). Thus, the average value of the dclink voltage can be expressed aswhere and are duty ratios of voltages and , respectively, and satisfy the following constraints:The localaveraged input currents are expressed aswhere is the localaveraged dclink current of . Combining (2), (3), and (4) with the condition of unit input power factor, the duty ratios are obtained bywhere is the sampling period. and are action times of voltages and .
Combining (2) and (5), the average value of the dclink voltage is
Thus, varies in each input segment. The respective minimum and maximum values of the average dclink voltage are
According to the above analysis, the switching states in each segment and the corresponding duty ratios are shown in Table 1.

For the fiveleg inverter stage, assume the expected output voltages are described bywhere and are the amplitude and angular frequency of the output phase voltage, respectively.
The distribution of output voltage space vector is shown in Figure 3(a), which includes thirty active vectors and two zero vectors ( and , not shown in Figure 3(a)). Each vector is represented by the set (, , , , and ), where () is defined as
(a) Distribution of output voltage space vector
(b) Generation of output reference voltage
There are six adjacent vectors in each sector that can be used to synthesize the reference output voltage vector. However, in order to obtain the maximum output reference voltage, only two adjacent maximum vectors and , and two medium vectors and , and zero vector are selected [22], as shown in Figure 3(b).
The reference output voltage vector can be described bywherewhere is the modulation index of the fiveleg inverter stage, . is the angle between the vector and the vector . . . , , , and and , , , and are action times and duty ratios of corresponding vector. is the ratio of the medium and maximum vector in the same direction. In order to ensure the output voltage is sinusoidal waveform, the value of should be equal to .
Suppose the output voltage is in sector I (, ), from (11), the sum of the duty ratios of the active vectors must be satisfied
From (11) and (12), the following inequality can be obtained:
On the left of (13), when the numerator takes the maximum value and the denominator takes the minimum value, (13) should also be established. That is,
From (7) and (14), the voltage transfer ratio (VTR) of the threetofivephase IMC is calculated as
To obtain the sinusoidal input and output waveforms, the switching pattern should produce an effective combination of the rectifier and inverter switching states. The input voltages in segment 1 and output voltages in sector I are taken as an example; the duty ratios of switching states within one sampling period are obtained by (5) and (11):
According to Figure 3(b), for the first half of the switching period, the vectors of the fiveleg inverter stage are switched by , and in reverse for the second half for the symmetrical scheme. The switching sequence of the two stages is shown in Figure 4. The selection principle of zero vectors, and , is to ensure the least switching number in each sampling period. . According to (16), the action time of each switching state is , , , , , , , , , , and . From Figure 4, the zero dclink current commutation is achieved in the rectifier stage [21].
2.3. Sector Transition Problem
The principle of the transition from one segment to the other adjacent segment is to ensure the least switching number.
In the rectifier stage, The states of six switches in rectifier stage are represented by the set (, , , , , and ), and = 1 denotes that the switch is ON state, and = 0 denotes that the switch is OFF state, where ; . The switching sequence in segment 1 is . In case of transit to segment 2, the switching sequence is . So, during the transition, the switch switches only once. From Figure 2(b), in case of transit from segment 2 to segment 3, the switch state remains unchanged. It is similar in other segments.
In the inverter stage, the switching sequence in sector I is . In case of the transit to the sector II, the switching sequence is . The switching sequence in other sectors is similar to that described above.
3. CMV Analysis in ThreetoFivePhase IMC
The principle of CMV when a fivephase AC motor is driven by the threetofivephase IMC is shown in Figure 5. is the leakage impedance between the load neutral point and the ground. The paths of CMV and leakage current are represented by the dashed line in Figure 5. Then, the equations can be obtained by KVL:where , , , , and are voltages between output phases and the ground. and are the equivalent resistance and inductance of the AC motor. Under the condition of sinusoidal and symmetrical output waveforms, the sum of output currents is equal to zero . From (17), The CMV can be expressed asAccording to the above analysis, it can be seen that the CMV is generated inevitably between the motor neutral point and the ground, when the motor is driven by fivephase converter. Different peak value of CMV is generated due to the different switching combinations, when the conventional modulation strategies in [11, 22] are applied. According to the basic principle of the conventional modulation strategy, taking the input voltage in segment 1 and the reference output voltage vector in sector I as an example, when the dclink voltage is and the vector is used in the fiveleg inverter stage, the output phases “A,” “B,” and “E” are connected to “p” pole of dcside (input phase “a”); “C” and “D” are connected to “n” pole of dcside (input phase “b”). Combining (18), The CMV generated at this time is calculated by , the value range of which is , . Thus, the peak value of CMV is times of the amplitude of input phase voltage. Other cases are similar to the above. The distribution of CMV at each switching combination is shown in Table 2. Similarly, the same method can be used to analyze the CMV of other sector combinations.

From Table 2, the peak value of CMV is the amplitude of input phase voltage when the zero vector is used in the fiveleg inverter stage. Then, the dclink is connected to an input phase with the maximum absolute value. The CMV, the peak value of which is equal to , is generated.
4. The CBPWM Method with CMV Reduction
By analyzing the switching sequence in Figure 4, the zero vectors in the inverter stage are assigned to the rectifier stage, equivalently, which are not considered in the inverter stage. Thus, the dclink voltage is synthesized by two larger line voltages and a zero voltage, which can be selected according to the absolute value of the input phase voltage. When the input voltage is in segments 1, 2, 7, and 8, the zero voltage is selected; the voltage is used in segments 3, 4, 9, and 10; and in segments 5, 6, 11, and 12, is used. The input voltage in segment 1 and the reference output voltage vector in sector I are taken as an example; the switching sequence is shown in Figures 6(a) and 6(b).
In terms of the change rate of CMV, the CMV is changed 16 times within one sampling period by using the improved modulation strategy. While it is 22 times and 18 times when using two zero vectors and one zero vector, respectively, under conventional modulation strategies.
According to (16), the action time of each switching state in Figure 6 is , , , , , , , , and .
In the rectifier stage, when the switching states are switched, the active vectors are used in the inverter stage. Thus, the commutation mode should be applied appropriately to ensure the safe commutation of switches in the rectifier stage.
According to the above analysis and Table 2, the peak value of CMV is not more than , so that it can be reduced to of the amplitude of the input phase voltage.
The modulation strategy is realized by complex division and combination of sectors, which is similar to the SVPWM strategy. In order to simplify the process, only one symmetrical triangular carrier signal is applied in this paper, which is described aswhere is the instantaneous value of the carrier signal.
4.1. Rectifier Stage Control
Figure 6(d) shows the principle to generate gate pulses for the rectifier stage. The two modulation signals and in Figure 6(c) are used to generate the gate pulses for rectifier stage. The two pulses and in Figure 6(d) are obtained by comparing two modulation signals to the carrier signal. The gate pulses for switches , , , and are calculated byThe gate pulses for other switches are and . The switching sequence for the rectifier stage, shown in Figure 6(a), is obtained by (20) and Figure 6(d).
From Figures 6(a) and 6(c), the durations and can be derived as
Combining (19) and (21), two modulation signals are obtained by
In other segments, the two modulation signals are similar to (22). In different input segments, they can be written aswhere and are two modulation signals for the rectifier stage. and .
4.2. Inverter Stage Control
In Figure 6(b), because the zero vectors are not considered in the inverter stage, the switches and keep ON state, while and keep OFF state within each sampling period in sector I, so that the switches of phases “B,” “C,” and “E” are modulated. In order to generate the gate pulse for the upper switch of each phase, two modulation signals are needed. Figure 6(e) shows the principle to generate the gate pulse for switch when the CBPWM method is used in the inverter stage. The two modulation signals, and , are used to generate the gate pulse for the upper switch of phase “E,” which is shown in Figure 6(c). The pulses and are obtained by comparing two modulation signals, and , respectively, with the symmetrical triangular signal . Then, the pulse for switch is shown in Figure 6(e). It is obtained by XOR function:
The switching sequence for output phase “E” is obtained by (24) and Figure 6(e).
From Figures 6(b) and 6(c), the durations and can be derived as
Combining (19) and (25), two modulation signals are obtained by
The two modulation signals of other phases are similar to (22) as well as in other sectors. Generally, the double modulation signals to generate gate pulse for the upper switch of phase “” () in the inverter stage are given bywhere and are two modulation signals of phase “” and is output voltage of phase “”.
In the inverter stage, the gate pulse of the lower switch of each phase has a complementary relationship with that of the upper switch. However, in the different sectors, the switches which keep ON state or OFF state continuously are different. Thus, the different modulation signals are needed, as shown in Table 3.

5. Simulation Results
In order to verify the feasibility of the proposed CBPWM method, the simulation model of threetofivephase IMC is established based on Matlab/Simulink. The parameters of the simulation model are shown in Table 4. The simulation results are shown in Figures 7 and 8.

(a) Input voltage and current of phase “a”
(b) Output adjacent linetoline voltage
(c) FFT analysis of
(d) Output fivephase current
(a) The CMV of conventional modulation strategy
(b) The CMV of the proposed CBPWM method
Figure 7 contains the simulation waveforms of the input voltage and input current , output linetoline voltage , FFT analysis of , and fivephase output current. From Figure 7(a), the input current becomes almost sinusoidal waveform due to the LC filter. However, the LC filter causes the displacement angle between the input voltage and current at the power supply. From Figures 7(b) and 7(c), the output linetoline voltage does not contain the loworder harmonic, and the output currents are sinusoidal waveforms in Figure 7(d). It can be confirmed that the sinusoidal output voltages and input currents are obtained by using proposed CBPWM method.
Figure 8 shows the CMV waveforms with the conventional modulation strategies, proposed in [11, 22], and the proposed CBPWM method, respectively. Obviously, the peak value of CMV in Figure 8(a) is 311 V which is equal to the amplitude of input phase voltage. And the peak value of CMV in Figure 8(b) is equal to about 224 V, which is 72% (about ) of the amplitude of input phase voltage. In other words, by using the proposed CBPWM method, the CMV is reduced by 28%. It is consistent with the theoretic analysis above.
6. Conclusion
In this paper, a CBPWM method to reduce CMV of threetofivephase IMC is proposed. To ensure the dclink is connected to an input phase with the minimum absolute value, the zero vectors are selected and arranged reasonably. Thus, the peak value of CMV can be reduced effectively, which is times of the amplitude of input phase voltage. The method is implemented by using only one symmetrical triangular carrier signal, which is simple and avoids the complexity of sector combination and lookup tables. Due to the zero vector is assigned to the rectifier stage, the switching times as well as the switching losses are reduced. The correctness of the theoretical analysis is verified by simulation.
Competing Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
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Copyright © 2016 Rutian Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.