Mathematical Problems in Engineering / 2018 / Article / Fig 5

Research Article

Neurospace Mapping Modeling for Packaged Transistors

Figure 5

Comparison of -parameters between measured data, coarse model, and proposed model for the LDMOS transistor at the typical work bias point (): (a) magnitude of , (b) phase of , (c) magnitude of , (d) phase of , (e) magnitude of , (f) phase of , (g) magnitude of , and (h) phase of .
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.