Research Article

Neurospace Mapping Modeling for Packaged Transistors

Table 2

Accuracy comparison of coarse model and proposed models for DC and S-parameter simulation.

ParameterCoarse Model 
Test Error (%)
Proposed Model 
Test Error (%)

1.010.85
21.612.18
25.873.12
23.813.97
36.683.79
10.292.02
4.992.07
24.182.01
40.402.19