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Mathematical Problems in Engineering
Volume 2018, Article ID 5216029, 8 pages
https://doi.org/10.1155/2018/5216029
Research Article

Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

1Chung Yuan Christian University, Taoyuan City, Taiwan
2Chien Hsin University of Science and Technology, Taoyuan City, Taiwan

Correspondence should be addressed to Cheng-Yuan Chang; wt.ude.ucyc@ycc

Received 4 November 2017; Revised 5 February 2018; Accepted 19 February 2018; Published 22 March 2018

Academic Editor: Ahmed Refaey

Copyright © 2018 Chiung-Wei Huang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We propose a prototype of field programmable gate array (FPGA) implementation for optimal pixel adjustment process (OPAP) algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC) to an FPGA board using RS232 interface for hardware processing. We firstly embed -bit secret message into each pixel of the cover image by the last-significant-bit (LSB) substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.