Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Figure 6

The experimental results of embedding “Field” in “Tulips.” (a) The cover image “Tulips” of size 1024 × 1024; (b) secret image “Field” of size 512 × 1024; (c) the stego image produced by both hardware structures.

(a)

(b)

(c)