Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Table 3

Comparison of execution time and speedup for embedding “Girl.”

Execution time (seconds)			Speedup
	Software	FPGA
1	0.116482	0.013110	≈8.88
2	0.122311	0.013110	≈9.33
3	0.145358	0.013110	≈11.09
4	0.204881	0.013110	≈15.63