Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Table 4

Device utilization of the proposed FPGA design.

System structure		Pixel-wised structure		10-pixel parallel structure
Hardware devices	Available	Used	Utilization	Used	Utilization
Slices	4650	270	5%	1980	43%
Slice flip flop	9312	239	2%	2390	20%
4 input LUTs	9312	340	3%	3400	30%
Bounded IOBs	232	4	1%	40	10%
BUFGMUXs	24	2	8%	20	80%
MUFT18X18SIOs	20	2	10%	20	100%