FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

<div>The Genesio–Tesi chaotic attractor in the phase plane with initial conditions <span class="nowrap"><svg height="17.2613pt" id="M146" style="vertical-align:-5.341099pt" version="1.1" viewbox="-0.0498162 -11.9202 203.624 17.2613" width="203.624pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M290 -163V-135C183 -126 181 -122 181 -44V583C181 662 184 666 290 675V703H120V-163H290Z"></path></g><g transform="matrix(.013,0,0,-0.013,4.485,0)"><path d="M536 404C536 423 520 448 491 448C445 448 398 404 308 283L286 338C255 416 242 448 217 448C182 448 138 402 92 341L111 321C149 368 169 378 178 378C188 378 198 363 214 320L254 212C185 117 138 65 107 65C98 65 85 69 82 75C79 82 73 86 65 86C44 86 23 60 23 39C23 7 44 -12 71 -12C119 -12 168 33 265 177L306 61C321 17 347 -12 373 -12C413 -12 465 33 507 96L491 119C459 84 432 60 413 60C395 60 378 92 358 148L321 250C341 279 369 310 389 332C417 363 439 382 456 382C466 382 475 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Mathematical Problems in Engineering

fig1

Figure 1

Figure 1: FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks 

Figure 1 | FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks 