FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

<div>(a) Bifurcation diagram of Liu system with varying parameter <span class="nowrap"><svg height="9.49473pt" id="M190" style="vertical-align:-0.2063999pt" version="1.1" viewbox="-0.0498162 -9.28833 6.21949 9.49473" width="6.21949pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M452 333C452 398 425 448 375 448C329 448 235 404 140 292H138L229 683C233 701 234 712 225 712C208 712 149 686 66 677L64 652H97C135 652 140 651 129 598L38 167C23 96 29 57 44 33C60 7 98 -12 132 -12C169 -12 232 3 290 41C383 102 452 223 452 333ZM365 316C365 199 308 87 239 49C221 39 200 35 183 35C137 35 99 70 112 163C116 191 123 215 129 233C190 316 290 392 330 392C348 392 365 372 365 316Z"></path></g></svg>.</span> (b) Bifurcation diagram of Liu system with varying parameter <span class="nowrap"><svg height="6.1673pt" id="M191" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 5.39742 6.1673" width="5.39742pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M383 397C383 424 344 448 299 448C244 448 172 409 132 375C66 319 23 227 23 146C23 42 74 -12 146 -12C208 -12 298 30 359 103L343 124C315 95 248 48 192 48C145 48 111 85 111 163C111 228 129 294 151 330C171 363 201 401 241 401C275 401 302 384 325 356C332 347 339 344 348 348C373 360 383 381 383 397Z"></path></g></svg>.</span></div>

Mathematical Problems in Engineering

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Figure 5

Figure 5: FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks 

Figure 5 | FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks 