FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

Table 2

FPGA chip resource usage for the Xilinx Zynq-7000 XC7Z020 FPGA chip (the resources used for both implementations are shown in the table).

	Genesio–Tesi			Liu
	Used	Total	Percent (%)	Used	Total	Percent (%)
Slice registers	24372	106400	22.9	24253	106400	22.8
Slice LUT	27543	53200	51.8	28550	53200	53.7
DSP48s	173	220	78.6	201	220	91.4
Block RAMs	103	140	73.6	103	140	73.6
Clock	40 MHz			40 MHz