FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

Table 4

Some FPGA-based implementations of chaotic systems over the last decade.

Reference and year	Brief description	Numerical representation	Integration method	Device
[44], 2009	3D Chen chaotic system	IEEE-754 FLP 32 bits	RK4	Xilinx Virtex-II XCV1000FG456-4
[45], 2011	A new hyperchaotic 4D system	–	RK4	Xilinx Virtex-II Pro XC2VP30
[47], 2013	Switching 3D chaotic systems	FXP 32 bits 16I16Q	Euler	Xilinx Virtex-II FPGA 2VP30FFG896-7
[46], 2015	A 3D chaotic system	IEEE-754 FLP 32 bits	RK4	Xilinx Virtex-6 XC6VLX550T-2FF1759
[48], 2017	Fractional-order chaotic system	FXP 32 bits	Tustin	Altera Cyclone IV EP4CE11529C7N
[38], 2018	Fractional-order complex networks with chaotic nodes	FXP 24 bits 4I20Q	Grünwald–Letnikov	Xilinx Zynq-7000 XC7Z020
[49], 2019	Fractional-order chaotic system	FXP 32 bits	Grünwald–Letnikov	Altera Cyclone IV GX FPGA DE2I-150
[50], 2019	The Lü–Chen 2002 chaotic system	FXP 32 bits 16I16Q	Heun	Xilinx Virtex-6 XC6VLX75T-3FF484
[51], 2019	A new 3D chaotic system	FXP 32 bits 7I25Q	Euler and RK4	Xilinx Virtex-6 XC6VLX75T-3FF484
[52], 2019	OFDM system using chaos	FXP 128 bits	Euler	—
Proposed	A tracking scheme (master and slave)	FXP 30 bits 7I23Q	Euler	Xilinx Zynq-7000 XC7Z020