FPGA Realization of Spherical Chaotic System with Application in Image Transmission

Table 2

Utilization of resources in spherical attractor implementation on Intel’s Stratix III and Xilinx’s Artix-7 AC701 FPGA boards.

Resources	FPGA 1: Intel Stratix III			FPGA 2: Xilinx Artix-7 AC701
	Available	Used	Utilization (%)	Available	Used	Utilization (%)
LUTs	270,400	10,261	4	215,360	13,228	10
Memory LUTs	135,200	0	0	46,200	0	0
Registers	270,400	192	<1	269,200	193	<1
I/O pins	744	97	13	400	97	24
Block RAMs	16,662,528	0	0	13,140,000	0	0
DSPs	576	368	64	208	208	28