FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

Table 1

Virtual machine intranet communication delay.

Item	VM	VP-SLAM	Resources	MDBP-ACO	Vector VM	Delay
LUT	3.43	1.76	1.75	1.42	3.39	2.78
Random	3.74	2.83	4.16	2.83	4.73	4.46
NC_MAX	1.64	2.9	2.45	4.81	3.14	2.96
FPGA	1.07	2.66	4.13	4.24	1.69	3.37
EFFD	2.02	1.16	6.53	6.38	1.51	4
Process mapping	5.7	2.28	4.74	1.73	2.86	6.8