FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

Table 3

Pin limit and sampling depth.

Item	FPGA	Delay	Process mapping	Virtual machine	VP-SLAM
Vector VM	3.8	1.73	2.79	1	1.06
EFFD	4.22	4.95	3.14	2.99	2.95
PMOC	2.03	1.48	5.11	2.14	4.78
FBG	2.07	4.5	1.9	2.81	2.71
InGaAs	6.79	5.15	6.07	6.31	5.6
Resources	5.61	6.3	5.87	1.24	5.61