Modelling and Simulation in Engineering

Volume 2014 (2014), Article ID 127359, 7 pages

http://dx.doi.org/10.1155/2014/127359

## Simulated Annealing Technique for Routing in a Rectangular Mesh Network

^{1}Department of Mathematical Sciences, Faculty of Science, Universiti Teknologi Malaysia (UTM), 81310 Johor Bahru, Johor, Malaysia^{2}Centre for Industrial and Applied Mathematics, Universiti Teknologi Malaysia (UTM), 81310 Johor Bahru, Johor, Malaysia

Received 21 July 2014; Revised 8 December 2014; Accepted 9 December 2014; Published 22 December 2014

Academic Editor: Min-Chie Chiu

Copyright © 2014 Noraziah Adzhar and Shaharuddin Salleh. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

In the process of automatic design for printed circuit boards (PCBs), the phase following cell placement is routing. On the other hand, routing process is a notoriously difficult problem, and even the simplest routing problem which consists of a set of two-pin nets is known to be NP-complete. In this research, our routing region is first tessellated into a uniform array of square cells. The ultimate goal for a routing problem is to achieve complete automatic routing with minimal need for any manual intervention. Therefore, shortest path for all connections needs to be established. While classical Dijkstra’s algorithm guarantees to find shortest path for a single net, each routed net will form obstacles for later paths. This will add complexities to route later nets and make its routing longer than the optimal path or sometimes impossible to complete. Today’s sequential routing often applies heuristic method to further refine the solution. Through this process, all nets will be rerouted in different order to improve the quality of routing. Because of this, we are motivated to apply simulated annealing, one of the metaheuristic methods to our routing model to produce better candidates of sequence.

#### 1. Introduction

In electronic design automation (EDA), wire routing or simply called routing is one of the most important steps in the design of VLSI integrated circuits and robot path planning. The connections for each pair of pins (sometimes called terminals or nodes) on the circuit must satisfy the design rules. High quality routing will give a great impact on the chip performance. Due it its importance and pervasive applications, researchers have shown a high interest in this problem and are studying extensively to improve the optimality and efficiency. An optimal routing should provide minimum cost, shortest distance, or lowest running time.

Suppose we are given a netlist and each net in the list consists of a pair of processing elements. This processing element is also sometimes referred to as node, processing node, or pin in the literature. For number of pins, there will be at most nets to be routed. However, in real problem, most of the time, the number of connections is usually less than nets because sometimes some of the pins are not assigned to be connected to any other pins. But we restrict ourselves to have maximum number of nets which is and propose a method to achieve 100% routing while satisfying the routing requirements.

However, it is almost impossible to have all nets routed in one layer especially when is large. In this paper, our goal is to propose a method to minimize layers in rectangular mesh network while satisfying the routing requirements. In order to do this, we need to maximize number of connections in each layer and thus it is important to have each net routed in shortest way. The complexity of a routing region is bounded by limitations of the number of processors and the energy level, and this energy level highly depends on the netlist.

Routing problem is an interesting topic and is being studied extensively among researchers. Several problems that have been addressed in this field include providing deadlock-free routing scheme [1], obstacle-aware routing problem with net length constraints [2], and also longest path for each net with the presence of obstacles [3]. Most of routing algorithm in this field is an extension of Lee’s algorithm [4–6]. Even though it guarantees to find minimum cost possible path if it exists, its searching nature based on wave propagation is slow. Therefore, we are motivated to propose another routing algorithm based on stochastic optimization using simulated annealing technique and Dijkstra’s algorithm to solve shortest path part of the problem. Our proposed routing algorithm can be applied to problems of any dimensions.

This paper can be organized as follows. Section 2 states the problem and discusses our routing layout model. Section 3 explains the shortest path problem which uses Dijkstra’s algorithm and the implementation of simulated annealing technique to the problem. The simulated work and whole results are discussed in Section 4. The paper concludes with conclusion in Section 5.

#### 2. Problem Statement

Routing in printed circuit board (PCB) is a process of determining and prescribing paths between various electronic components in order to establish a connection between given source point and its target. Routing in modern chip is a notoriously difficult problem, and even the simplest routing problem which consists of a set of two-pin nets is known to be NP-complete [7].

In this problem, our routing region is assumed to be divided uniformly into square cells and each cell contains pins. Unless stated otherwise, is assumed to be 1. With focus on wiring, we shall assume the location of pins has been specified. This process is as illustrated in Figure 1.