Schedulability Analysis for Rate Monotonic Algorithm-Shortest Job First Using UML-RT

<table class="table-group" id="tab1"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left">Capsule</td><td align="center">Input ports</td><td align="center">Output ports</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">gentask</td><td align="center">gin</td><td align="center">gout</td></tr><tr><td align="left">scheduler</td><td align="center">p1in, p2in, p3in, and sin</td><td align="center">p1out, p2out, p3out, and sout</td></tr><tr><td align="left">processor1</td><td align="center">pin11</td><td align="center">pout11</td></tr><tr><td align="left">processor2</td><td align="center">pin22</td><td align="center">pout22</td></tr><tr><td align="left">processor3</td><td align="center">pin33</td><td align="center">pout33</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Ports and capsules used in modelling multiprocessor architecture.

Modelling and Simulation in Engineering

tab1

Table 1

Table 1: Schedulability Analysis for Rate Monotonic Algorithm-Shortest Job First Using UML-RT 