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Modelling and Simulation in Engineering
Volume 2014, Article ID 635803, 7 pages
http://dx.doi.org/10.1155/2014/635803
Research Article

Modeling of Temperature-Dependent Noise in Silicon Nanowire FETs including Self-Heating Effects

SKP Engineering College, Tiruvannamalai, Tamil Nadu 606 611, India

Received 7 January 2014; Accepted 23 April 2014; Published 21 May 2014

Academic Editor: Agostino Bruzzone

Copyright © 2014 P. Anandan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. D. Suk, S.-Y. Lee, S.-M. Kim et al., “High performance 5 nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability,” in Proceedings of the International Electron Devices Meeting (IEDM '05), pp. 717–720, Washington, DC, USA, 2005.
  2. N. Singh, F. Y. Lim, W. W. Fang et al., “Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance,” in Proceedings of the International Electron Devices Meeting (IEDM '06), pp. 547–550, 2006.
  3. Y. Tian, R. Huang, Y. Wang et al., “New self-aligned silicon nanowire transistors on bulk substrate fabricated by epi-free compatible CMOS technology: process integration, experimental characterization of carrier transport and low frequency noise,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '07), pp. 895–898, Washington, DC, USA, December 2007. View at Publisher · View at Google Scholar
  4. Y. Jiang, T. Y. Liow, N. Singh et al., “Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts,” in Proceedings of the Symposium on VLSI Technology Digest of Technical Papers (VLSIT '08), pp. 34–35, June 2008.
  5. D. S. Kim, Y. C. Jung, M. Y. Park et al., “Electrical characteristics of the back-gated bottom-up silicon nanowire field effect transistor,” Nanotechnology, IEEE Transactions on, vol. 7, no. 6, pp. 683–687, 2008. View at Publisher · View at Google Scholar
  6. J. W. Jeon, B.-G. Park, J.-D. Lee, and H.-C. Shin, “Analytical noise parameter model of short-channel RF MOSFETs,” Journal of Semiconductor Technology and Science, vol. 7, no. 2, pp. 88–93, 2007. View at Publisher · View at Google Scholar
  7. S. Asgaran, M. J. Deen, and C. Chen, “Analytical modeling of MOSFETs channel noise and noise parameters,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2109–2114, 2004. View at Publisher · View at Google Scholar · View at Scopus
  8. G. Tan, C.-H. Chen, B. Hung, P. Lei, and C.-S. Yeh, “Channel thermal noise and its scaling impact on deep sub-100 nm MOSFETs,” in Proceedings of the 21st International Conference on Noise and Fluctuations (ICNF '11), pp. 356–359, Toronto, Canada, June 2011. View at Publisher · View at Google Scholar · View at Scopus
  9. F. D. Agostino and D. Quercia, “Short-channel effects in MOSFETs,” in Introduction to VLSI design (EECS 467), 2000. View at Google Scholar
  10. J. W. Jeon, B.-G. Park, J.-D. Lee, and H.-C. Shin, “An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects,” Solid-State Electronics, vol. 51, no. 7, pp. 1034–1038, 2007. View at Publisher · View at Google Scholar
  11. J. Lee, J. Jeon, J. Kim, B. Park, J. D. Lee, and H. Shin, “Prediction of channel thermal noise in twin silicon nanowire MOSFET (TSNWFET),” in Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT '08), pp. 61–63, Beijing, China, October 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. T. Ytterdal, Y. Cheng, and T. Fjeldly, Device Modeling for Analog & RF CMOS Circuit Design, John Wiley & Sons, New York, NY, USA, 2003.
  13. W. Jin, S. K. H. Fung, W. Liu, P. C. H. Chan, and C. Hu, “Self-heating characterization for SOI MOSFET based on AC output conductance,” in Proceedings of the International Electron Devices Meeting (IEDM '99), pp. 175–178, Washington, DC, USA, December 2007. View at Publisher · View at Google Scholar
  14. R. Huang, R. S. Wang, J. Zhuge et al., “Self-heating effect and characteristic variability of gate-all-around silicon nanowire transistors for highly-scaled CMOS technology (invited),” in Proceedings of the IEEE International SOI Conference (SOI '10), pp. 1–4, San Diego, Calif, USA, October 2010. View at Publisher · View at Google Scholar
  15. W. Shockley, J. A. Copeland, and R. P. James, “The impedance field method of noise calculation in active semiconductor devices,” in Quantum Theory of Atoms, Molecules and the Solid State, P. O. Loewdin, Ed., pp. 537–563, Academic Press, New York, NY, USA, 1966. View at Google Scholar
  16. F. Bonani, G. Ghione, M. R. Pinto, and R. K. Smith, “An efficient approach to noise analysis through multidimensional physics-based models,” IEEE Transactions on Electron Devices, vol. 45, no. 1, pp. 261–269, 1998. View at Publisher · View at Google Scholar · View at Scopus
  17. J. P. Nougier, “Fluctuations and noise of hot carriers in semiconductor materials and devices,” IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 2034–2049, 1994. View at Publisher · View at Google Scholar · View at Scopus
  18. A. Kunzmann, “Simulation of noise in semiconductor devices,” Tech. Rep. 98/7, Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland, 1998. View at Google Scholar