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Modelling and Simulation in Engineering
Volume 2014, Article ID 705929, 11 pages
http://dx.doi.org/10.1155/2014/705929
Research Article

Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

1Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai 600 044, India
2Department of Instrumentation Engineering, Madras Institute of Technology, Anna University, Chennai 600 044, India

Received 28 June 2013; Revised 4 October 2013; Accepted 18 October 2013; Published 13 February 2014

Academic Editor: Zeki Ayag

Copyright © 2014 S. Ewins Pon Pushpa and Manamalli Devasigamani. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The key for adopting the utilization-based schedulability test is to derive the utilization bound. Given the computation times, this paper proposes two utilization bound algorithms to derive interrelease times for nonpreemptive periodic tasks, using a new priority scheme, “Rate Monotonic Algorithm-Shortest Job First.” The obtained task set possesses the advantage of Rate Monotonic Algorithm and Shortest Job First priority scheme. Further, the task set is tested for schedulability, by first deriving a general schedulability condition from “problem window” analysis and, a necessary and sufficient schedulability condition for a task to be scheduled, at any release time are also derived. As a technical contribution, success ratio and effective processor utilization are analyzed for our proposed utilization bound algorithms on a uniprocessor architecture modeled using UML-RT.