Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td align="left">Capsules</td><td align="center">Input ports</td><td align="center">Output ports</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">Task generator</td><td align="center">—</td><td align="center">Gout</td></tr><tr><td align="left">Scheduler</td><td align="center">Sin</td><td align="center">Sout</td></tr><tr><td align="left">Processor</td><td align="center">Pin1</td><td align="center">Pout1</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Modelling and Simulation in Engineering

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Table 2

Table 2: Utilization Bound Scheduling Analysis for Nonpreemptive Uniprocessor Architecture Using UML-RT 