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Modelling and Simulation in Engineering
Volume 2017 (2017), Article ID 6261404, 10 pages
https://doi.org/10.1155/2017/6261404
Research Article

Analytical Modelling and Verification of Bus-Clamping Modulation Technique for Switched-Capacitor Converter

1Department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
2University Road, Teliarganj Township, Allahabad, Uttar Pradesh 211004, India

Correspondence should be addressed to Akbar Ahmad

Received 31 August 2016; Accepted 15 January 2017; Published 8 February 2017

Academic Editor: Nikos D. Lagaros

Copyright © 2017 Amarnath Yalavarthi and Akbar Ahmad. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Space vector modulation techniques have advantages of high output voltages and reduced harmonic content as they utilize the dc bus effectively. Bus-clamped pulse width modulation classified in space vector techniques has the ability to reduce the switching losses of the converter and has reduced harmonic distortion. This paper provides mathematical analysis for 60-degree bus-clamping strategy to obtain the complete closed-form solution for finding the harmonic coefficients using double Fourier integral expression. The effectiveness of the bus-clamped approach on switched capacitor based multilevel inverter has been shown with comparison to Sinusoidal PWM. The DSP controller TMS320F240 has been chosen for the real-time implementation of 60-degree bus-clamping modulation technique. Simulation and experimental results of the prototype are presented for RL load at different modulation indices showing the superiority of the configuration to cascaded multilevel inverter.