Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Table 2

Previous study on NC-FinFET.

Highlights	Tfin (nm)	Tox (nm)	Hfin (nm)	Lg (nm)	SS (mV/decade)	Year [reference]
Sub-10 nm NC-FinFET is analyzed operating at 0.25 V	3	0.7	—	9	—	2017 [18]
Investigation of CMOS logic circuits using NC-FinFET	8	—	34	30	—	2017 [19]
FE capacitor of Sub-60 mV/decade NC-FinFET with sub-10 nm	10	1.4	40	90	36.31	2017 [20]
NC-FinFET with minimal hysteresis of 0.48Vand sub-20 mV/dec SS	40	1.4	40	70	<20	2017 [21]
Design and evaluation of performance of SRAM using 7 nm-node NC-FinFET	6.5	1	32	21	—	2017 [22]
Analysis of fin-LER variability in NC-FinFET	9.6	2	25	22	—	2017 [23]
TCAD simulation to design NC-FinFET to avoid instability of NC state	4	0.5	—	20	48	2017 [24]
Analysis of process variations impact on NC-FinFET	6.5	1	32	21	—	2018 [25]
Analysis of spacer designs for FinFET and NC-FinFET	6	0.9	42	16	65.6	2019 [26]
Ge NC-FinFET in presence of fixed trap charges is analyzed	8	1	9	20	—	2019 [27]
Improved SS and drain current in NC-FinFET	7; 7	1; 1	40; 40	500; 20	34.5; 53	2019 [41]
Relation between TFE and stability of 6 T NC-FinFET-based SRAM cell	8	0.65	42	20	—	2019 [28]
GIDL issue in NC-FinFET is analyzed	7	0.9	50	20	75	2020 [29]