FPGA Implementation of Digital Images Watermarking System Based on Discrete Haar Wavelet Transform

Table 1

Consumed hardware resources in insertion and extraction steps resources.

Resources	Insertion Step			Extraction Step
	Used	Available	Percentage	Used	Available	Percentage
Number of register slices	1,536	32,640	4%	619	32,640	2%
Number of slice LUT	2,092	32,640	6%	1,002	32,640	3%
Number of used logic blocks	2,494	32,640	8%	532	32,640	1%
Number of DSP48	1	48	2%	1	48	2%
Number of BRAM	9	148	6%	12	148	8%
	Maximum frequency =224 MHz			Maximum frequency =232 MHz