Review Article
Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures
Table 1
Cache capacity and latency.
| Model | Microarchitecture | L1 size (K) | L1 latency | L2 size | L2 latency | L3 size (M) | L3 latency |
| i7-6900K | Bradwell | 64 | 4 | 256 | 12 | 20 | 59 | i7-6700 | Skylake | 64 | 4 | 256 | 12 | 8 | 42 | i7-4770 | Haswell | 64 | 4 | 256 | 12 | 8 | 36 | i7-3770 | Ivy Bridge | 64 | 4 | 256 | 12 | 8 | 29.9 | E5-2699 | Bradwell | 64 | 4 | 256 | 12 | 55 | 65 | i3-2120 | Sandy Bridge | 64 | 4 | 256 | 12 | 3 | 27.9 |
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