Review Article
Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures
Table 2
Research studies on cache-based side-channel attacks.
| Attacks | Patterns | Cache types | Range | Target |
| [14] | Prime + Probe | L1-D | Core | OpenSSL(0.9.7c) RSA | [2] | Prime + Probe | L1-D | Core | AES | [5, 23] | Prime + Probe | L1-D | Core | OpenSSL(0.9.8) AES | [21] | Prime + Probe | L1-I | Core | OpenSSL(0.9.8d) RSA | [6] | Prime + Probe | L1-I | Core | OpenSSL(0.9.8e) RSA | [8] | Evict +time | LLC | CPU | Kernel memory | [20] | Flush + Reload | LLC | CPU | OpenSSL(0.9.8n) AES | [30] | Flush + Reload | LLC | CPU | GnuPG(1.4.13) RSA | [4] | Flush + Reload | LLC | CPU/VM | OpenSSL(1.0.1f) AES | [31–34] | Flush + Reload | LLC | CPU | OpenSSL(1.0.1e) ECDSA | [9] | Flush + Reload | LLC | CPU/VM | User activities | [35] | Flush + Reload | LLC | CPU | TLS andDTLS | [36] | Flush + Reload | LLC | CPU | Keyboard input | [37] | Prime + Probe | LLC | CPU | GnuPG(1.4.13/1.4.18) ElGamal | [22] | Flush + Reload | LLC | CPU | OpenSSL DSA | [38] | Prime + Probe | LLC | CPU | AES | [39] | Flush + Flush | LLC | Core | AES T-table | [16] | Invalidate + Transfer | — | System | Open SSL AES/libgcrypt ElGamal | [12, 13, 17] | Flush + reload/evict + time | LLC | CPU | Memory isolation | [40, 41] | Prime + Probe | LLC | CPU/enclave | RSA |
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