A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Table 1

RISC-V base opcode map, inst[1 : 0] = 11.

inst[4 : 2]	000	001	010	011	100	101	110	111 ( 32b)
inst[6 : 5]
00	LOAD	LOAD-FP	custom-0	MISC-MEM	OP-IMM	AUIPC	OP-IMM-32	48b
01	STORE	STORE-FP	custom-1	AMO	OP	LUI	OP-32	64b
10	MADD	MSUB	NMSUB	NMADD	OP-FP	reserved	custom-2/rv128	48b
11	BRANCH	JALR	reserved	JAL	SYSTEM	reserved	custom-3/rv128	80b