A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

Table 2

The proposed definition of coprocessor instructions.

	KEY-UPDATE	INIT		Loop
		CBC-INIT	CMAC-INIT
funct7[2 : 0]	000	001	101	011
rs1	Read address for key	Read address for plaintext		Length of plaintext
rs2	(Disable)	Write address for result		(Disable)
rd	(Disable)	(Disable)		(Disable)