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Scientific Programming
Volume 5 (1996), Issue 2, Pages 161-171

Compiler-Enforced Cache Coherence Using a Functional Language

Rich Wolski1 and David Cann2

1Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093, USA
2Convex Computer Corporation, P.O. Box 833851, Richardson, TX 75083, USA

Received 19 April 1995; Accepted 19 June 1995

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The cost of hardware cache coherence, both in terms of execution delay and operational cost, is substantial for scalable systems. Fortunately, compiler-generated cache management can reduce program serialization due to cache contention; increase execution performance; and reduce the cost of parallel systems by eliminating the need for more expensive hardware support. In this article, we use the Sisal functional language system as a vehicle to implement and investigate automatic, compiler-based cache management. We describe our implementation of Sisal for the IBM Power/4. The Power/4, briefly available as a product, represents an early attempt to build a shared memory machine that relies strictly on the language system for cache coherence. We discuss the issues associated with deterministic execution and program correctness on a system without hardware coherence, and demonstrate how Sisal (as a functional language) is able to address those issues.