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Scientific Programming
Volume 13, Issue 3, Pages 239-253

JIST: Just-In-Time Scheduling Translation for Parallel Processors

Giovanni Agosta, Stefano Crespi Reghizzi, Gerlando Falauto, and Martino Sykora

Politecnico di Milano, Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32 - 20133 Milano, Italy

Received 26 December 2005; Accepted 26 December 2005

Copyright © 2005 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.