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Scientific Programming
Volume 2015, Article ID 197843, 16 pages
http://dx.doi.org/10.1155/2015/197843
Research Article

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

1Mohammad Ali Jinnah University, Islamabad, Pakistan
2Streaming Networks (Pvt.) Ltd., Islamabad, Pakistan
3Mohammad Ali Jinnah University, Karachi, Pakistan

Received 15 May 2015; Revised 22 September 2015; Accepted 4 October 2015

Academic Editor: Bormin Huang

Copyright © 2015 Muhammad Asif et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. I. Werda, T. Dammak, T. Grandpierre, M. A. B. Ayed, and N. Masmoudi, “Real-time H.264/AVC baseline decoder implementation on TMS320C6416,” Journal of Real-Time Image Processing, vol. 7, no. 4, pp. 215–232, 2012. View at Publisher · View at Google Scholar · View at Scopus
  2. K. Babionitakis, G. Doumenis, G. Georgakarakos et al., “A real-time H.264/AVC VLSI encoder architecture,” Journal of Real-Time Image Processing, vol. 3, no. 1-2, pp. 43–59, 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. Z. Wei, K. L. Tang, and K. N. Ngan, “Implementation of H.264 on mobile device,” IEEE Transactions on Consumer Electronics, vol. 53, no. 3, pp. 1109–1116, 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. T. Wiegand, H. Schwarz, A. Joch, F. Kossentini, and G. J. Sullivan, “Rate-constrained coder control and comparison of video coding standards,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 688–703, 2003. View at Publisher · View at Google Scholar · View at Scopus
  5. Q. Tang and P. Nasiopoulos, “Efficient motion re-estimation with rate-distortion optimization for MPEG-2 to H.264/AVC transcoding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 20, no. 2, pp. 262–274, 2010. View at Publisher · View at Google Scholar · View at Scopus
  6. B. La, M. Eom, and Y. Choe, “Dominant edge direction based fast intra mode decision in the H.264/AVC encoder,” Journal of Zhejiang University: Science A, vol. 10, no. 6, pp. 767–777, 2009. View at Publisher · View at Google Scholar · View at Scopus
  7. M. Asif, M. Farooq, and I. A. Taj, “Optimized implementation of motion compensation for H.264 decoder,” in Proceedings of the 5th International Conference on Computer Sciences and Convergence Information Technology (ICCIT '10), pp. 216–221, IEEE, Seoul, Republic of Korea, December 2010. View at Publisher · View at Google Scholar · View at Scopus
  8. S. Momcilovic, N. Roma, and L. Sousa, “Exploiting task and data parallelism for advanced video coding on hybrid CPU + GPU platforms,” Journal of Real-Time Image Processing, pp. 1–17, 2013. View at Publisher · View at Google Scholar · View at Scopus
  9. M. Alvanos, G. Tzenakis, D. S. Nikolopoulos, and A. Bilas, “Task-based parallel H.264 video encoding for explicit communication architectures,” in Proceedings of the 11th International Conference on Embedded Computer Systems (SAMOS '11), pp. 217–224, IEEE, Samos, Greece, July 2011. View at Publisher · View at Google Scholar · View at Scopus
  10. S. Sankaraiah, H. S. Lam, C. Eswaran, and J. Abdullah, “Gop level parallelism on h.264 video encoder for multicore architecture,” in Proceedings of the International Conference on Circuits, System and Simulation (ICCSS '11), vol. 7, pp. 127–133, IPCSIT, May 2011.
  11. H. K. Nguyen, P. Cao, X.-X. Wang et al., “Hardware software co-design of H.264 baseline encoder on coarse-grained dynamically reconfigurable computing system-on-chip,” IEICE Transactions on Information and Systems, vol. E96-D, no. 3, pp. 601–615, 2013. View at Publisher · View at Google Scholar · View at Scopus
  12. M. Asif, S. Majeed, I. A. Taj, M. Bin Ahmed, and S. M. Ziauddin, “Exploiting MB level parallelism in H.264/AVC encoder for multi-core platform,” in Proceedings of the IEEE/ACS 11th International Conference on Computer Systems and Applications (AICCSA '14), pp. 125–130, Doha, Qatar, November 2014. View at Publisher · View at Google Scholar
  13. K. S. Aw, S. M. Goh, K. H. Goh, T. K. Chiew, and J. Y. Tham, “Real-time HD video encoding on DSP,” in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications (ICIEA '10), pp. 1992–1995, IEEE, Taichung, Taiwan, June 2010. View at Publisher · View at Google Scholar · View at Scopus
  14. D.-T. Lin and C.-Y. Yang, “H.264/AVC video encoder realization and acceleration on TI DM642 DSP,” in Advances in Image and Video Technology: Third Pacific Rim Symposium, PSIVT 2009, Tokyo, Japan, January 13–16, 2009. Proceedings, vol. 5414 of Lecture Notes in Computer Science, pp. 910–920, Springer, Berlin, Germany, 2009. View at Publisher · View at Google Scholar
  15. D. Schneider, M. Jeub, Z. Jun, and S. Li, “Advanced H.264/AVC encoder optimizations on a TMS320DM642 digital signal processor,” in Proceedings of the 16th International Conference on Digital Signal Processing (DSP '09), pp. 1–14, July 2009. View at Publisher · View at Google Scholar · View at Scopus
  16. X. He, X. Fang, C. Wang, and S. Goto, “Parallel HD encoding on CELL,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '09), pp. 1065–1068, IEEE, Taipei, Taiwan, May 2009. View at Publisher · View at Google Scholar
  17. C.-T. Lu and H.-M. Hang, “Multiview encoder parallelized fast search realization on NVIDIA CUDA,” in Proceedings of the IEEE Visual Communications and Image Processing (VCIP '11), pp. 1–4, Tainan, Taiwan, November 2011. View at Publisher · View at Google Scholar · View at Scopus
  18. M. Schwalb, R. Ewerth, and B. Freisleben, “Fast motion estimation on graphics hardware for h.264 video encoding,” IEEE Transactions on Multimedia, vol. 11, no. 1, pp. 1–10, 2009. View at Publisher · View at Google Scholar · View at Scopus
  19. N.-M. Cheung, X. Fan, O. Au, and M.-C. Kung, “Video coding on multicore graphics processors,” IEEE Signal Processing Magazine, vol. 27, no. 2, pp. 79–89, 2010. View at Publisher · View at Google Scholar · View at Scopus
  20. A. Azevedo, B. Juurlink, C. Meenderinck et al., “A highly scalable parallel implementation of H.264,” Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC), vol. 4, no. 2, pp. 111–134, 2011. View at Google Scholar
  21. S. Momcilovic, N. Roma, and L. Sousa, “Multi-level parallelization of advanced video coding on hybrid CPU/GPU platform,” in Proceedings of the 10th International Workshop on Algorithms, pp. 165–174, Rhodes Islands, Greece, August 2012.
  22. Ingenic Semiconductor, JZ4770 VPU Programming Manual, Ingenic Semiconductor, Beijing, China, 2011.
  23. Ingenic Semiconductor Co, JZ4770 Data Sheet, Ingenic Semiconductor Co, 2011.
  24. Ingenic Semiconductor, MXU Instruction Usage Guide, Ingenic Semiconductor, Beijing, China, 2011.
  25. E. B. Van Der Tol, E. G. T. Jaspers, and R. H. Gelderblom, “Mapping of H.264 decoding on a multiprocessor architecture,” in Image and Video Communications and Processing, vol. 5022 of Proceedings of SPIE, pp. 707–718, Santa Clara, Calif, USA, January 2003. View at Publisher · View at Google Scholar · View at Scopus
  26. x264, http://www.videolan.org/developers/x264.html.