HPC Programming on Intel Many-Integrated-Core Hardware with MAGMA Port to Xeon Phi

Figure 1

(a) MIC MAGMA programming model with a LLAPI server mediating requests between the host CPU and the Xeon Phi device. (b) DLA algorithm as a collection of BLAS-based tasks and their dependencies. The algorithm’s critical path is, in general, scheduled on the CPUs and large data-parallel tasks on the Xeon Phi.

(a)

(b)