Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0012a.svgz" name="937694.fig.0012a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>100 patterns</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0012b.svgz" name="937694.fig.0012b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>5,000 patterns</td></tr><tr class="fig-image" id="c"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0012c.svgz" name="937694.fig.0012c" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(c) </b>50,000 patterns</td></tr></table>

<div>Throughput (Gbps) comparisons using P-2 implementation.</div>

Scientific Programming

fig12

Figure 12

Figure 12: Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips 