Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0016a.svgz" name="937694.fig.0016a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>P-1 implementation</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0016b.svgz" name="937694.fig.0016b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>P-2 implementation</td></tr></table>

<div>Throughput comparisons for<b> Dict_Input_S</b> using P-1 and P-2 implementations.</div>

Scientific Programming

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Figure 16

Figure 16: Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips 