Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

<div>AC machine implemented as a DFA for a set of patterns <svg height="11.5564pt" id="M22" style="vertical-align:-2.26807pt" version="1.1" viewbox="-0.0498162 -9.28833 4.62754 11.5564" width="4.62754pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M293 -169V-141C218 -131 209 -90 209 -44C209 19 222 85 222 152C222 207 198 255 139 269V273C199 286 222 334 222 388C222 454 209 523 209 588C209 632 218 671 293 681V709C234 709 148 695 148 577C147 513 155 438 155 372C155 337 152 291 64 285V256C152 250 155 204 155 169C156 105 148 31 148 -41C148 -157 234 -169 293 -169Z" id="g113-124"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="347" vert-adv-y="347"></glyph.data></g></svg>he, she, his, and hers}.</div>

Scientific Programming

fig4

Figure 4

Figure 4: Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips 