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Scientific Programming
Volume 2016 (2016), Article ID 1907521, 11 pages
http://dx.doi.org/10.1155/2016/1907521
Research Article

Bus Based Synchronization Method for CHIPPER Based NoC

SASTRA University, Thanjavur, Tamil Nadu 613 401, India

Received 28 January 2016; Revised 12 May 2016; Accepted 7 June 2016

Academic Editor: Meng Guo

Copyright © 2016 D. Muralidharan and R. Muthaiah. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. W. J. Dally and B. Towels, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of the Design Automation Conference (DAC '01), pp. 684–689, Las Vegas, Nev, USA, June 2001.
  2. L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78, 2002. View at Publisher · View at Google Scholar · View at Scopus
  3. S. Kumar, A. Jantsch, J.-P. Soininen et al., “A network on chip architecture and design methodology,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 105–112, Pittsburgh, Pa, USA, April 2002. View at Publisher · View at Google Scholar
  4. L. Benini and D. Bertozzi, “Network on chip architectures and design methods,” IEE Proceedings—Computers and Digital Techniques, vol. 152, no. 2, pp. 261–272, 2005. View at Google Scholar
  5. W.-C. Tsai, Y.-C. Lan, Y.-H. Hu, and S.-J. Chen, “Networks on chips: structure and design methodologies,” Journal of Electrical and Computer Engineering, vol. 2012, Article ID 509465, 15 pages, 2012. View at Publisher · View at Google Scholar · View at Scopus
  6. W. J. Dally and B. Towels, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers, 2003.
  7. P. Ezhumalai, A. Chilambuchelvan, and C. Arun, “Novel NoC topology construction for high-performance communications,” Journal of Computer Networks and Communications, Article ID 405697, 6 pages, 2011. View at Publisher · View at Google Scholar · View at Scopus
  8. Z. Lu and A. Jantsch, “TDM virtual-circuit configuration for network-on-chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 8, pp. 1021–1034, 2008. View at Publisher · View at Google Scholar · View at Scopus
  9. T. T. Ye, L. Benini, and G. De Micheli, “Analysis of power consumption on switch fabrics in network routers,” in Proceedings of the 39th Annual Design Automation Conference (DAC '02), pp. 524–529, IEEE, New Orleans, La, USA, June 2002. View at Scopus
  10. C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. S. Yousif, and C. R. Das, “ViChaR: a dynamic virtual channel regulator for network-on-chip routers,” in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '06), pp. 333–346, Orlando, Fla, USA, December 2006. View at Publisher · View at Google Scholar
  11. Y. Zhang, R. Morris Jr., and A. K. Kodi, “Design of a performance enhanced and power reduced dual-crossbar Network-on-Chip (NoC) architecture,” Microprocessors and Microsystems, vol. 35, no. 2, pp. 110–118, 2011. View at Publisher · View at Google Scholar · View at Scopus
  12. T.-Y. Lee and C.-H. Huang, “Design of smart power-saving architecture for network on chip,” VLSI Design, vol. 2014, Article ID 531653, 10 pages, 2014. View at Publisher · View at Google Scholar · View at Scopus
  13. T. Moscibroda and O. Mutlu, “A case for bufferless routing in on-chip networks,” in Proceedings of the 36th International Symposium on Computer Architecture (ISCA '09), pp. 1–12, Austin, Tex, USA, June 2009.
  14. P. Baran, “On distributed communications networks,” IEEE Transactions on Communications Systems, vol. 12, no. 1, pp. 1–9, 1964. View at Publisher · View at Google Scholar · View at Scopus
  15. A. Monemi, C. Y. Ooi, and M. N. Marsono, “Low latency Network-on-Chip router microarchitecture using request masking technique,” International Journal of Reconfigurable Computing, vol. 2015, Article ID 570836, 13 pages, 2015. View at Publisher · View at Google Scholar · View at Scopus
  16. J. Lin, X. Lin, and L. Tang, “Making-a-stop: a new bufferless routing algorithm for on-chip network,” Journal of Parallel and Distributed Computing, vol. 72, no. 4, pp. 515–524, 2012. View at Publisher · View at Google Scholar · View at Scopus
  17. C. Fallin, G. Nazario, X. Yu, K. Chang, R. Ausavarungnirun, and O. Mutlu, “MinBD: minimally-buffered deflection routing for energy-efficient interconnect,” in Proceedings of the 6th IEEE/ACM International Symposium on Networks-on-Chip (NoCS '12), pp. 1–10, Lyngby, Denmark, May 2012. View at Publisher · View at Google Scholar · View at Scopus
  18. C. Fallin, C. Craik, and O. Mutlu, “CHIPPER: a low-complexity bufferless deflection router,” in Proceedings of the 17th International Symposium on High-Performance Computer Architecture (HPCA '11), pp. 144–155, San Antonio, Tex, USA, February 2011. View at Publisher · View at Google Scholar · View at Scopus
  19. I. Z. Stojanovic, M. D. Jovanovic, and G. L. Djordjevic, “Low-cost port allocation scheme for minimizing deflections in bufferless on-chip networks,” in Proceedings of the 21st Telecommunications Forum (TELFOR '13), pp. 357–360, IEEE, Belgrade, Serbia, November 2013. View at Publisher · View at Google Scholar · View at Scopus