SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing

Table 5

Summary of fault testing experiment on SEDC-based fault tolerant 4-bit adder.

	(a) Total errors at the output of the adder	(b) BEs	(c) Detected BEs	(d) UEs	(e) Detected UEs	(f) Total detected errors	(g) Total undetected errors
Total	1748	252	120	1496	1496	1616	132
Percentage (%)	100	14.42 w.r.t. (a)	47.62 w.r.t. (b)	85.58 w.r.t. (a)	100 w.r.t (d)	92.45 w.r.t. (a)	7.55 w.r.t. (a)