First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 3

ZU9 FPGA resource utilization for the 333 MHz reduced interconnect designs using 12 matrix-vector IP blocks for single and double precision.

	BRAM_18K	DSP48E	FF	LUT
Double-precision IP block	8	10	23199	7203
Single-precision IP block	4	3	11934	6391
Single-precision IP block resource relative to double precision (%)	50	30	51	89
Double-precision 12-block Vivado design	816	120	302606	204616
Single-precision 12-block Vivado design	792	36	162726	131758
ZU9 FPGA available resource	912	2520	548160	274080
Single-precision Vivado design resource relative to double precision (%)	97	30	54	64