First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 4

Performance in Gflop/s using different numbers of matrix-vector IP blocks of Design 1 (full) and Design 2 (reduced) for single and double precision on the UltraScale+ FPGA at different clock frequencies.

Number of matrix-vector IP blocks	Design 2 (reduced interconnect)				Design 1 (full interconnect)
	Single precision	Double precision			Double precision
	333 MHz	333 MHz	250 MHz	100 MHz	333 MHz	250 MHz	100 MHz
1	515.7	510.6	386.3	157.9	483.1	362.0	148.3
2	1025.5	1016.2	768.7	312.7	950.7	720.7	292.6
3	1512.0	1496.4	1140.2	463.9	1385.9	1048.5	432.7
4	2008.8	1995.7	1508.6	616.8	1808.4	1370.5	562.0
5	2511.3	2477.7	1889.8	772.9	2253.3	1711.1	705.3
6	2947.1	2900.2	2208.0	907.0	2645.9	2007.9	828.2
7	3414.7	3351.6	2545.8	1047.3	3033.7	2314.7	960.4
8	3956.5	3862.6	2944.9	1209.2	3508.4	2666.1	1105.4
9	4390.0	4286.3	3275.1	1351.7	—	—	—
10	4761.8	4629.6	3527.9	1465.6	—	—	—
11	5274.2	5040.3	3875.9	1610.0	—	—	—
12	5580.1	5338.8	4084.6	1707.9	—	—	—