First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 6

Maximum clock frequency at which Design 2 still operates correctly for different numbers of matrix-vector blocks.

Number of matrix-vector blocks	Maximum clock frequency (MHz)	Matrix-vector performance (Gflop/s)
1	450	0.688
4	400	2.372
8	333	3.863
12	333	5.339