Sunita Chandrasekaran

Barbara Chapman

Xinmin Tian

Yonghong Yan

Programming Models, Languages, and Compilers for Manycore and Heterogeneous Architectures

Performance degradation due to nonuniform data access latencies has worsened on NUMA systems and can now be felt on-chip in manycore processors. Distributing data across NUMA nodes and manycore processor caches is necessary to reduce the impact of nonuniform latencies. However, techniques for distributing data are error-prone and fragile and require low-level architectural knowledge. Existing task scheduling policies favor quick load-balancing at the expense of locality and ignore NUMA node/manycore cache access latencies while scheduling. Locality-aware scheduling, in conjunction with or as a replacement for existing scheduling, is necessary to minimize NUMA effects and sustain performance. We present a data distribution and locality-aware scheduling technique for task-based OpenMP programs executing on NUMA systems and manycore processors. Our technique relieves the programmer from thinking of NUMA system/manycore processor architecture details by delegating data distribution to the runtime system and uses task data dependence information to guide the scheduling of OpenMP tasks to reduce data stall times. We demonstrate our technique on a four-socket AMD Opteron machine with eight NUMA nodes and on the TILEPro64 processor and identify that data distribution and locality-aware task scheduling improve performance up to 69&#x25; for scientific benchmarks compared to default policies and yet provide an architecture-oblivious approach for programmers.

Ananya Muddukrishna

Peter A. Jonsson

Mats Brorsson

Locality-Aware Task Scheduling and Data Distribution for OpenMP Programs on NUMA Systems and Manycore Processors

Utilizing heterogeneous platforms for computation has become a general trend, making the portability issue important. OpenCL (Open Computing Language) serves this purpose by enabling portable execution on heterogeneous architectures. However, unpredictable performance variation on different platforms has become a burden for programmers who write OpenCL applications. This is especially true for conventional multicore CPUs, since the performance of general OpenCL applications on CPUs lags behind the performance of their counterparts written in the conventional parallel programming model for CPUs. In this paper, we evaluate the performance of OpenCL applications on out-of-order multicore CPUs from the architectural perspective. We evaluate OpenCL applications on various aspects, including API overhead, scheduling overhead, instruction-level parallelism, address space, data location, data locality, and vectorization, comparing OpenCL to conventional parallel programming models for CPUs. Our evaluation indicates unique performance characteristics of OpenCL applications and also provides insight into the optimization metrics for better performance on CPUs.

Joo Hwan Lee

Nimit Nigania

Hyesoon Kim

Kaushik Patel

Hyojong Kim

OpenCL Performance Evaluation on Modern Multicore CPUs

Existing studies show that using single GPU can lead to obtaining significant performance gains. We should be able to achieve further performance speedup if we use more than one GPU. Heterogeneous processors consisting of multiple CPUs and GPUs offer immense potential and are often considered as a leading candidate for porting complex scientific applications. Unfortunately programming heterogeneous systems requires more effort than what is required for traditional multicore systems. Directive-based programming approaches are being widely adopted since they make it easy to use<svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-2.18977pt" id="M1" height="11.4781pt" version="1.1" viewBox="-0.0498162 -9.28833 5.69754 11.4781" width="5.69754pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g50-48" d="M381 704H317L48 -163H112L381 704Z"/></g></svg>port<svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-2.18977pt" id="M2" height="11.4781pt" version="1.1" viewBox="-0.0498162 -9.28833 5.69754 11.4781" width="5.69754pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><use xlink:href="#g50-48"/></g></svg>maintain application code. OpenMP and OpenACC are two popular models used to port applications to accelerators. However, neither of the models provides support for multiple GPUs. A plausible solution is to use combination of OpenMP and OpenACC that forms a hybrid model; however, building this model has its own limitations due to lack of necessary compilers&#x2019; support. Moreover, the model also lacks support for direct device-to-device communication. To overcome these limitations, an alternate strategy is to extend OpenACC by proposing and developing extensions that follow a task-based implementation for supporting multiple GPUs. We critically analyze the applicability of the hybrid model approach and evaluate the proposed strategy using several case studies and demonstrate their effectiveness.

Rengan Xu

Xiaonan Tian

Multi-GPU Support on Single Node Using Directive-Based Programming Model

In standard OpenCL programming, hosts are supposed to control their compute devices. Since compute devices are dedicated to kernel computation, only hosts can execute several kinds of data transfers such as internode communication and file access. These data transfers require one host to simultaneously play two or more roles due to the need for collaboration between the host and devices. The codes for such data transfers are likely to be system-specific, resulting in low portability. This paper proposes an OpenCL extension that incorporates such data transfers into the OpenCL event management mechanism. Unlike the current OpenCL standard, the main thread running on the host is not blocked to serialize dependent operations. Hence, an application can easily use the opportunities to overlap parallel activities of hosts and compute devices. In addition, the implementation details of data transfers are hidden behind the extension, and application programmers can use the optimized data transfers without any tricky programming techniques. The evaluation results show that the proposed extension can use the optimized data transfer implementation and thereby increase the sustained data transfer performance by about 18&#x25; for a real application accessing a big data file.

Hiroyuki Takizawa

Shoichi Hirasawa

Makoto Sugawara

Isaac Gelado

Hiroaki Kobayashi

Wen-mei W. Hwu

Optimized Data Transfers Based on the OpenCL Event Management Mechanism

Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the Intel C/C++ and Fortran production compilers for Intel Xeon Phi coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel Xeon Phi coprocessor. We also demonstrate a 2000x performance speedup from the seamless integration of SIMD vectorization and parallelization.

Hideki Saito

Serguei V. Preis

Eric N. Garcia

Sergey S. Kozhukhov

Matt Masten

Aleksei G. Cherkasov

Nikolay Panchenko

Effective SIMD Vectorization for Intel Xeon Phi Coprocessors

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<p><em>Scientific Programming </em>provides a forum for research results in, and practical experience with, software engineering environments, tools, languages, and models of computation aimed specifically at supporting scientific and engineering computing.</p>


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<p>Chief Editor&nbsp;Professor Tramontana&nbsp;is based at the University of Catania and his research primarily concerns the areas of software engineering and distributed systems.</p>


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Scientific Programming

Programming Models, Languages, and Compilers for Manycore and Heterogeneous Architectures

Programming Models, Languages, and Compilers for Manycore and Heterogeneous Architectures

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