Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Table 1

Summary of the hardware resource utilization for the proposed architecture targeted to a Xilinx Spartan-6 LX45 device for different number of instances of the HGW module.

Resource utilization (total available)	1-HGW	2-HGW	4-HGW
Slice registers (54576)	75	150	216
Slice LUTs (27288)	258	566	910
LUTs used as logic (27288)	159	368	518
LUTs as memory (6408)	96	192	384
RAMB16BWERs (116)	0	0	0
RAMB8BWERs (232)	0	0	0
Maximum frequency	250 MHz	232 MHz	215 MHz