Design of Efficient Full Adder in Quantum-Dot Cellular Automata

Table 2

Comparison of the recent 1-bit full adder.

Design	Cell count	Area 𝜇m^2	Clock no. cycle	MV gate no.	Inv gate no.
In [16]	135	0.14	1.25	3 (3 MV)	2
In [15]	108	0.10	1	3 (3 MV)	2
In [17], type I	79	0.05	1.25	2 (3 MV); 1 (5 MV)	2
In [17], type II	51	0.03	0.75	1 (3 MV); 1 (5 MV)	2
This work	31	0.01	0.50	1 (3 MV); 1 (5 MV)	0