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The Scientific World Journal
Volume 2013, Article ID 913038, 11 pages
Research Article

Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures

1School of Software, Beijing Institute of Technology, Beijing, China
2School of Information and Electronics, Beijing Institute of Technology, Beijing, China

Received 1 May 2013; Accepted 28 June 2013

Academic Editors: E. Denti, J. Montero, and G. Wei

Copyright © 2013 Haijing Tang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Srividya Rajaraman, Pritam Sirpotdar, Abhijeet Wavare, and A B Patki, “Multithreading implementation in a single core TMS320C6713 DSP,” 2014 International Conference on Advances in Communication and Computing Technologies (ICACACT 2014), pp. 1–5, . View at Publisher · View at Google Scholar
  • Sishu Zeng, Haijing Tang, and Xu Yang, “Scheduling instructions for enhanced performance and energy efficiency on a clustered architecture with applications in big-data sensor networks,” Journal of Low Power Electronics, vol. 12, no. 1, pp. 1–8, 2016. View at Publisher · View at Google Scholar
  • Hu He, Xu Yang, and Yanjun Zhang, “On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage,” The Computer Journal, 2017. View at Publisher · View at Google Scholar