Research Article | Open Access
A Novel Sample Based Quadrature Phase Shift Keying Demodulator
This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10−6, whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.
Quadrature Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communication system due to its ability to transmit twice the data rate for a given bandwidth . An ideal QPSK signal where the in-phase and quadrature components are in quadrature (90°) and have equal amplitude cannot be obtained, according to  due to the noise presence in local oscillator, DC offset in mixer, and phase imbalance in power combiner and mixers. At the same time, the transmitted QPSK signal frequency, , may also vary by due to Doppler effect . A practical QPSK signal, , will contain gain error , phase error (), and frequency shift (), as given in where is the carrier frequency, is the energy per symbol, is the symbol period, and is the carrier phase. While the gain error can be easily reduced with automatic gain controller (AGC), the phase noise and frequency shift are more complicated and can tremendously affect the performance of the system. The performance of a conventional coherent demodulator starts to degrade at phase noise of 3.6° . Previous works attempted to solve both phase error and frequency shift problems by using feedback control loop and feed-forward compensation technique, only adding more complexity to the demodulator circuit .
Typical QPSK demodulator needs SNR of 10 dB to produce BER of . Even though the SNR value presumed as low in wireless signal transmission, for a system such as satellite and mobile devices where their operations are power limited, this is an issue that needs attention . Components used in the conventional QPSK demodulator for the demodulation process such as VCO, LPF, and mixers increase the power consumption of the system. Thus, this paper proposed a new technique that is simple, consumes less power, and is robust to the phase noise.
This paper is structured as follows. Section 1 gives an introduction to readers about this journal. Section 2 briefly explains the proposed new QPSK demodulator, followed by Section 3 showing MATLAB simulation carried out on the proposed architecture. In Section 4 results obtained from the simulation are provided and discussed in detail. Finally our results are concluded and some details about our future work are given in Section 5.
2. Proposed QPSK Demodulator
The proposed QPSK demodulator uses polarity difference from digitized QPSK signal for the demodulation process and is given a new code name 8S-QPSK. Figure 1 shows the complete block diagram for the proposed design where it consists of analog to digital converter (ADC), first in first out (FIFO), lookup table (LUT), and comparators.
Digitizing is a process used in ADC to convert the incoming analog signal to digital signal based on the ADC sampling rate. In the proposed QPSK demodulator the incoming signal is sampled 8 times of the incoming signal frequency. A sample is produced for every rising clock of the ADC circuit for a total number of 8 samples. A decision is made on every 2 samples to be classified as positive and negative samples based on the sample’s polarities. This will eventually produce 4 different polarities for a QPSK signal and they are different for every QPSK symbol as shown in Table 1.
The QPSK phases represent a group of 2 bits data. The phases are produced at modulation level according to the inputs bits to the sinusoidal carrier [7, 8]. Once the phases are identified, the data can be recovered immediately.
3. MATLAB Simulation
The whole demodulation process starts with sampling of the QPSK signal from the signal recovery block by using the sample and hold circuit block. The sample and hold block will convert the continuous QPSK signal, , into discrete signal, , as given by where is the number of samples and is the quantization level. The maximum range of the ADC voltage is centered on the reference voltage 0 v. The chosen transmitted carrier frequency was 5 MHz because it is a frequently used bandwidth in wireless systems . Therefore the sampling clock frequency used in sample and hold block was set to 8 times the incoming frequency which is 40 MHz. The sampling clock is set by using pulse generator where the period of the pulse can be programmed. A group, , of 8 samples, , are produced for every phase of a QPSK symbol as given by Continuously, from the odd samples, of , a decision is made and sorted according to their polarities, , as given by The sign block is used after the sampling process to rearrange the sampled data according to the polarity. Figure 2 shows in detail the sampling and grouping process.
The series of polarities samples need to be changed into a parallel of matrixes so that it can be compared with each of the group data stored inside the LUT. A buffer with output size of four elements is used to redistribute the pulses from the sign block. Each pulse with positive and negative polarity has period and needs to be grouped into four elements with period of as given by This is crucial since only four complete pulses which have period equal to can determine a combinational group of data represented by the QPSK signal. Figure 3 shows an example on how the buffer redistributes the received data.
3.2. Lookup Table
A total number of four lookup tables (LUT) are used to store the 4 combinational pulses which were predetermined earlier. The data inside each LUT is stored in the form of matrixes as shown in Figure 1. To do so, arrays of four constants data are grouped and transposed. Every LUT will be compared constantly with the buffer output which is also in the matrix. The sample time inside the LUT was set at so that one LUT can be compared with four pulses which have the same period. The LUT was not stacked in any order since the modulated data was in random order.
A comparator is used to compare the data stored inside the LUT with the data from the buffer. If a group of four datasets from the buffer match with any LUT, this means that the QPSK symbol was sampled correctly and the dibits are able to be retrieved. Four embedded MATLAB function blocks are used for the comparator which contains a MATLAB function of , where the and represent the data from the buffer and LUT, respectively.
4. Results and Discussions
A MATLAB Simulink simulation was carried out on both of the QPSK demodulation techniques and compared to identify their performances with and without phase error. BER has been used as a main performance indicator in this project. The satisfactory BER values obtained for every different noise level in Simulink simulation are compiled in tables and represented in graphical forms. A total amount of 20 Mb of data was used as input to the modulator for every case in obtaining the BER values. At the same time, a study was carried out to evaluate the proposed design operating power consumption.
4.1. Performance Analysis on Signal Power with AWGN
In this section, the QPSK signal is demodulated with the proposed and conventional demodulator with different levels of SNR starting from −2 dB until as high as 6 dB through AWGN channel. This analysis demonstrates the ability of the proposed architecture to withstand the white Gaussian noise compared to the conventional architecture. To validate the performance of the system a 95% of confidence level of the confidence interval test was used for every simulation. The confidence interval test was carried out by using MATLAB built-in function where it requires data such as BER, the total number of input data, and range of SNR to calculate the interval level and the maximum and minimum number of BER [10, 11]. The data compiled for both demodulation schemes are represented graphically in Figure 4. The exponential curve fit has been used to interpolate the log-log scale dataset so that the graph will resemble the water fall curve shape .
It can be seen from Figure 4, for a particular BER (e.g., ), that the proposed technique has a lower SNR compared to the conventional technique. The noise power, , for both signals can be determined using (6) and this noise power will be used together with the SNR value to give the signal power, , as depicted in (7). Table 2 shows the power comparison for both techniques at BER of : The result shows that, for a particular BER, the proposed method can reduce the signal detection power up to 74.9% when compared with conventional method and lower SNR values are obtained for every BER value. This is due to the architecture of the proposed design which no longer employs coherent detection technique in the demodulation process.
4.2. Performance Analysis on Signal Power with Phase Error
To determine the ability of the proposed design to tolerate high phase error in AWGN channel, a simulation has been performed to obtained data for BER with respect to SNR for 8S-QPSK and conventional QPSK schemes with phase errors of 9°, 18°, and 27°. The results obtained are shown in graphical form in Figure 5. SNR values for BER of are taken from each graph and shown in Table 3 for comparison. As for phase error of 18° and 27° for conventional QPSK schemes, the SNR values are only shown until 6 dB in Figure 6. However, the other two SNR values, 8 and 11.6 dB, have been successfully obtained in the simulation conducted. In this simulation, confidence interval test is not included since the upper and lower limit values tend to overlap with each other between the curves.
The proposed demodulator shows power gain of 5.2 dB for 9° and 5.8 dB for 18° and 27° phase errors when compared to conventional QPSK demodulator. This achievement is obtained because the samples used to identify the signal phase, , are taken for every 45 degrees. Thus, if any variation happened on the signal between the sampling period, it is not going to affect the sample value obtained. As in Figure 6, the samples, , represent ideal QPSK signal, , and phase error QPSK signal by 45 degrees, . As for both signals, samples obtained at any sampling time, , give the same positive or negative values regarding the phase error. The signals shown in Figure 6 are QPSK signals for , 45° generated at high SNR value, and 10 dB to give an idea on how the phase error alone will affect the sampling process:
However, when SNR values for 8S-QPSK from Tables 3 and 2 are compared, it shows that there are power increments from 1.2 dB to 6.8 dB to obtain the same BER value. The degradation on the performance happened due to the dependency of the proposed design on the amplitude of the incoming signal. The white Gaussian noise will cause voltage fluctuation on the incoming signal and thus will cause the polarity change in the sampling process. In conventional method, the phase error with the presents of white noise cannot be corrected or rectified with high SNR value as in proposed method.
To demonstrate the phase error effect on conventional demodulator, gain error and frequency shift have been removed from the incoming QPSK signal as in (1) to ease the calculation. At the same time, the phase error only was included into one of two local oscillators, sine carrier. This is to show clearly how phase error on one of the carriers can cause the demodulated data to be shifted in time domain when odd and even data were data merged together.
It can be seen that, by mixing the QPSK signal with the sine carrier as shown in (9), it produces two different terms. First, a sine signal with twice the frequency, phase shifted and half amplitude from the incoming signal. Second, another sine signal which varies according to the phase error and half the input amplitude signal. The first signal will be superimposed on second signal which acts like dc offset signal. By using an LPF after the mixing process, the first high frequency term, , can be filtered out and the remaining term given in the expression will cause the odd data to be shifted in time domain by . Figure 7 shows output from mixing the QPSK and sine carrier, filtered I-channel signal with LPF, and odd and even data obtained from I channel and Q-channel. The steps involved in obtaining the even data are not shown here but they are the same as in (9). The only difference is the sine carrier substituted by cosine carrier without any phase error:
It has been proven that a small variation (3.6°) of phase error will seriously affect the demodulation process and cause the data to be misinterpreted. On the other hand, the new architecture uses polarity of samples to recognize the QPSK signal symbols correctly and is not bounded with mixing signal issue mentioned earlier.
4.3. Analysis of Power Consumption
Power consumption estimation has been conducted for the proposed design based on the power consumed by individual components obtained from literature as shown in Table 4. For each one of the components, maximum and a minimum values are taken into consideration from various references so that it will give a rough idea for the total power consumption that can be expected.
The number of components used in the simulation is as follows: 1 unit of ADC, 16 units of comparator, 8 units of LUT, and 2 units of FIFO as shown in Figure 1. The following calculation shows the maximum and minimum power consumption for the proposed design:
It can be seen that the power consumption of the proposed design is between 0.788 mW and 64.233 mW which is significantly reduced compared to the 206 mW  consumed by the conventional QPSK. The reduction of the power consumption is between 68.8 and 99.6%.
5. Conclusion and Future Work
A novel architecture for QPSK demodulator has been proposed and demonstrated promising results. The results obtained for both demodulation schemes do not include any error correction coding, phase, and frequency error detection technique. The new demodulation technique uses samples polarity from ADC to identify the QPSK symbols. This indirectly eliminates the use of VCO, a component that contributes to the phase and frequency distortion. The new architecture consumes almost 74.9% less power for signal detection in AWGN channel without any phase error and 50 to 89.6% when phase error is presented. On top of that, the proposed design is also expected to consume 68.8 to 99.6% less power and significant size reduction compared with conventional architecture.
As for future work, channel selection method, error correction coding, and signal locking mechanism for sampling starting time will be included to further evaluate the proposed architecture. Hardware implementation on Virtex 6 FPGA board has been planned for performance measurement and verification.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
- D. Roddy, Satellite Communications, McGraw Hill, New York, NY, USA, 4th edition, 2006.
- D. Master Easton, J. Snowdon, and D. Spencer, Quadrature phase error in receivers [Thesis of Science], University of Southampton, 2008.
- M. Sobol, “The Doppler Effect and Digital Video Broadcasting,” 17 pages, 2007, http://user.informatik.uni-goettingen.de/~seminar/dvb/TheDopplerEffect_V4_eng.pdf.
- K. Z. Chen and A. Q. Hu, “MPSK demodulation algorithm based on pattern recognition,” in Proceedings of the 2008 IEEE International Conference on Neural Networks & Signal Processing, pp. 182–186, June 2008.
- Y. Liu and C. Tao, “Feedback compensation algorithm for BPSK/QPSK carrier synchronization,” Radioengineering, vol. 19, no. 1, pp. 149–154, 2010.
- T. S. Tuli, N. G. Orr, and R. E. Zee, “Low cost ground station design for nanosatellite missions,” in Proceedings of the North American Space Symposium, pp. 1–9, 2006.
- A. M. Moubark, M. A. M. Ali, H. Sanusi, S. M. Ali, and N. Zainal, “Simple QPSK modulator implemented in virtex 6 FPGA board for satellite ground station,” in Proceeding of the International Conference on Computer Design, pp. 131–135, 2011.
- A. M. Moubark, M. A. Mohd Ali, H. Sanusi, and S. M. Ali, “FPGA implementation of low power digital QPSK modulator using verilog HDL,” Journal of Applied Sciences, vol. 13, no. 3, pp. 385–392, 2013.
- R. Frank, “Evolution of air interface,” 2012, http://www.ieeeottawa.ca/aicn/wpcontent/uploads/2012/05/Evolution-of-the-Air-Interface-v0.3.pdf.
- http://www.mathworks.com/help/comm/ug/bit-error- rate-ber.html#bsvziy0.
- Y. Fan, A versatile FPGA-based high speed bit error rate testing scheme [Master of Engineering], Department of Electrical and Computer Engineering McGill Univerity, Montreal, Canada, 2003.
- C. Langton, “Intuitive Guide to Principles of Communications,” 2002, http://complextoreal.com/wp-content/uploads/2013/01/linkbud.pdf.
- M. Subba Reddy and S. Tipu Rahaman, An Effective 6-bit Flash ADC using Low Power CMOS Technology.
- R. Thirugnanam, D. S. Ha, and S. S. Choi, “Design of a 4-bit 1.4 GSamples/s low power folding ADC for DS-CDMA UWB transceivers,” in Proceedings of the IEEE International Conference on Ultra-Wideband (ICU '05), pp. 536–541, Zürich, Switzerland, September 2005.
- M. F. Snoeij, A. J. P. Theuwissen, and J. H. Huijsing, “A 1.8 V 3.2μW Comparator for use in a CMOS imager column-level single-slope ADC,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), pp. 6162–6165, May 2005.
- P. Velrajkumar, C. Senthilpari, G. Ramanamurthy, and E. K. Wong, “Proposed adder and modified LUT bit parallel unrolled CORDIC circuit for an application in mobile robots,” Asian Journal of Scientific Research, vol. 6, no. 4, pp. 666–678, 2013.
- D. Kumar, P. Kumar, and M. Pattanaik, “Performance analysis of 90 nm Look up Table (LUT) for low power application,” in Proceedings of the 13th Euromicro Conference on Digital System Design, pp. 404–407, September 2010.
- M. Chang, P. Huang, and W. Hwang, “A robust ultra-low power asynchronous FIFO memory with self-adaptive power control,” in Proceedings of the IEEE International SOC Conference, pp. 175–178, September 2008.
- M. E. S. Elrabaa, “A new FIFO design enabling fully-synchronous on-chip data communication network,” in Proceedings of the Saudi International Electronics, Communications and Photonics Conference (SIECPC '11), pp. 1–6, Riyadh, Saudi Arabia, April 2011.
- M. Chun, “BPSK, QPSK, 8-PSK Demodulator for FPGA 5 pages,” http://www.innovative-dsp.com/support/datasheets/IP-PSK_DEMOD4.pdf.
Copyright © 2014 Asraf Mohamed Moubark and Sawal Hamid Md Ali. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.