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The Scientific World Journal
Volume 2014 (2014), Article ID 107831, 7 pages
http://dx.doi.org/10.1155/2014/107831
Research Article

A Novel Sample Based Quadrature Phase Shift Keying Demodulator

Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia

Received 13 April 2014; Revised 21 July 2014; Accepted 22 July 2014; Published 14 August 2014

Academic Editor: Ramesh Pokharel

Copyright © 2014 Asraf Mohamed Moubark and Sawal Hamid Md Ali. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. D. Roddy, Satellite Communications, McGraw Hill, New York, NY, USA, 4th edition, 2006.
  2. D. Master Easton, J. Snowdon, and D. Spencer, Quadrature phase error in receivers [Thesis of Science], University of Southampton, 2008.
  3. M. Sobol, “The Doppler Effect and Digital Video Broadcasting,” 17 pages, 2007, http://user.informatik.uni-goettingen.de/~seminar/dvb/TheDopplerEffect_V4_eng.pdf.
  4. K. Z. Chen and A. Q. Hu, “MPSK demodulation algorithm based on pattern recognition,” in Proceedings of the 2008 IEEE International Conference on Neural Networks & Signal Processing, pp. 182–186, June 2008. View at Publisher · View at Google Scholar · View at Scopus
  5. Y. Liu and C. Tao, “Feedback compensation algorithm for BPSK/QPSK carrier synchronization,” Radioengineering, vol. 19, no. 1, pp. 149–154, 2010. View at Google Scholar · View at Scopus
  6. T. S. Tuli, N. G. Orr, and R. E. Zee, “Low cost ground station design for nanosatellite missions,” in Proceedings of the North American Space Symposium, pp. 1–9, 2006.
  7. A. M. Moubark, M. A. M. Ali, H. Sanusi, S. M. Ali, and N. Zainal, “Simple QPSK modulator implemented in virtex 6 FPGA board for satellite ground station,” in Proceeding of the International Conference on Computer Design, pp. 131–135, 2011.
  8. A. M. Moubark, M. A. Mohd Ali, H. Sanusi, and S. M. Ali, “FPGA implementation of low power digital QPSK modulator using verilog HDL,” Journal of Applied Sciences, vol. 13, no. 3, pp. 385–392, 2013. View at Publisher · View at Google Scholar · View at Scopus
  9. R. Frank, “Evolution of air interface,” 2012, http://www.ieeeottawa.ca/aicn/wpcontent/uploads/2012/05/Evolution-of-the-Air-Interface-v0.3.pdf.
  10. http://www.mathworks.com/help/comm/ug/bit-error- rate-ber.html#bsvziy0.
  11. Y. Fan, A versatile FPGA-based high speed bit error rate testing scheme [Master of Engineering], Department of Electrical and Computer Engineering McGill Univerity, Montreal, Canada, 2003.
  12. C. Langton, “Intuitive Guide to Principles of Communications,” 2002, http://complextoreal.com/wp-content/uploads/2013/01/linkbud.pdf.
  13. M. Subba Reddy and S. Tipu Rahaman, An Effective 6-bit Flash ADC using Low Power CMOS Technology.
  14. R. Thirugnanam, D. S. Ha, and S. S. Choi, “Design of a 4-bit 1.4 GSamples/s low power folding ADC for DS-CDMA UWB transceivers,” in Proceedings of the IEEE International Conference on Ultra-Wideband (ICU '05), pp. 536–541, Zürich, Switzerland, September 2005. View at Scopus
  15. M. F. Snoeij, A. J. P. Theuwissen, and J. H. Huijsing, “A 1.8 V 3.2μW Comparator for use in a CMOS imager column-level single-slope ADC,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), pp. 6162–6165, May 2005. View at Publisher · View at Google Scholar · View at Scopus
  16. P. Velrajkumar, C. Senthilpari, G. Ramanamurthy, and E. K. Wong, “Proposed adder and modified LUT bit parallel unrolled CORDIC circuit for an application in mobile robots,” Asian Journal of Scientific Research, vol. 6, no. 4, pp. 666–678, 2013. View at Publisher · View at Google Scholar · View at Scopus
  17. D. Kumar, P. Kumar, and M. Pattanaik, “Performance analysis of 90 nm Look up Table (LUT) for low power application,” in Proceedings of the 13th Euromicro Conference on Digital System Design, pp. 404–407, September 2010. View at Publisher · View at Google Scholar · View at Scopus
  18. M. Chang, P. Huang, and W. Hwang, “A robust ultra-low power asynchronous FIFO memory with self-adaptive power control,” in Proceedings of the IEEE International SOC Conference, pp. 175–178, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  19. M. E. S. Elrabaa, “A new FIFO design enabling fully-synchronous on-chip data communication network,” in Proceedings of the Saudi International Electronics, Communications and Photonics Conference (SIECPC '11), pp. 1–6, Riyadh, Saudi Arabia, April 2011. View at Publisher · View at Google Scholar · View at Scopus
  20. M. Chun, “BPSK, QPSK, 8-PSK Demodulator for FPGA 5 pages,” http://www.innovative-dsp.com/support/datasheets/IP-PSK_DEMOD4.pdf.