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The Scientific World Journal
Volume 2014, Article ID 164059, 15 pages
Research Article

Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

1University of Castilla-La Mancha, 13071 Ciudad Real, Spain
2Electronics Department, Polytechnic Faculty, University of Mons, Mons, Belgium

Received 21 August 2013; Accepted 30 October 2013; Published 6 February 2014

Academic Editors: R. de J. Romero-Troncoso, W. Su, Y.-B. Yuan, and Y. Zhang

Copyright © 2014 Julio Dondo Gazzano et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.